In a conventional thin-film transistor array substrate, with reference to FIG. 1, the thin-film transistor array substrate includes: a base substrate 110, a buffering layer 120, a gate electrode 131, a first storage electrode 132, a gate insulation layer 140, a metal oxide active layer 150, an etching barrier layer 160, a source electrode 171, a drain electrode 172, a second storage electrode 173, a passivation layer 180 and a pixel electrode 190. Wherein, the gate insulation layer 140 is provided with a storage through hole corresponding to the first storage electrode 132. The first storage electrode 132, the etching barrier layer 160 and the second storage electrode 173 form a storage capacitor.
In the above structure, forming the gate electrode 131 and the first storage electrode 132 requires one mask. Forming the gate insulation layer 160 requires one mask. Forming the source electrode 171, the drain electrode 172 and the second storage electrode 173 requires one mask. Forming the passivation layer 180 requires one mask. Forming a pixel electrode 190 requires one mask. Accordingly, the entire thin-film transistor array substrate requires 7 masks such that the number of the mask is higher, the cost is higher and the process is complex.